Modern digital electronic computers include a number of cooperating sequential logic circuits that each perform several routine operations, and are each controlled by derivatives of a common clock signal. The clock signals should be synchronized at predetermined locations within the system to help optimize computer function. Although the individual clock signals may have a common source, they often do not arrive at their intended destinations in proper synchronism, for example due to variations in signal propagation delay for each destination. Thus, combining several complex sequential logic circuits within a system presents a challenge with respect to synchronizing the time frames between the respective circuits therein.
Because synchronous sequential logic circuits change states at the rising or falling edge of a synchronous clock signal, proper circuit operation often demands that any external input signals to the synchronous sequential logic circuit generate valid inputs that occur with the proper set up time and hold time requirements relative to the designated clock edge. However, in a system including sequential logic circuits having a master system (or board) clock that operates the several diverse system chip circuits, there is often a problem with skew (different amounts of delay in different portions of the device) between the system clock and the destination clock signals propagating through the various circuits.
As higher density programmable logic devices (PLDs) become available, on-chip clock distribution becomes more important to the integrity and performance of the designs implemented in these devices. Unfortunately, with the advent of high-density PLDs, such as a field programmable gate array (FPGA), difficulties in managing clock delay and clock skew associated with these devices has become substantial. Many existing solutions for these problems, such as hardwired clock trees, are less effective for the high density PLDs found in today's programmable logic market. As integration levels of microelectronic circuits and system complexity continues to increase, the routing or distribution of a master system (or board) clock has become even more critical. The problem is also exacerbated as clock rates increase.
A common solution to these problems is the incorporation of a clock and data recovery system (CDR), also known as a programmable clock manager (PCM), into the PLDs themselves. A PCM may be used to adjust the clock phase and clock duty cycle for system clocks found in most chips. In general, a PCM compares an incoming master clock signal and a feedback data signal in order to generate an output clock signal based on a comparison of phase and/or frequency of the two input signals. Conventional PCMs may be found in either phase-locked loop (PLL) or delay-locked loop (DLL) architecture to assist in synchronizing clock signals in the PLD. Although DLL circuitry may be used to resolve some of the problems in today's PLDs, employing a voltage controlled oscillator (VCO) to create a PLL architecture has continued to gain popularity among device designers.
A VCO generally adjusts the various signals, such that the edges of the internal clock signals are aligned with those of a master clock signal, even though the time frame of each signal is thereby shifted. The PLL architecture provides feedback that is used to nullify clock distribution delays within the chip by comparing the phase of a master clock signal with that of a feedback signal. The difference between the two signals is used in a feedback control system to bring the first and second signals into a fixed phase relation. Logical elements, such as an AND gate and a divider, logically combine the master clock signal with the feedback signal to provide a synchronization signal for the chip circuits. More specifically, the master clock signal is compared with the feedback signal and a reference (synchronization) signal is generated in response to the difference. Delay circuitry may be used to produce delays in the output clock signal based on a selected delay time, depending on the application of the output clock signal. Alternatively, delay compensation may be used to synchronize the master clock and feedback signals based on the reference signal. In this way, all circuits within the chip receive synchronous clock signals and clock signal skew is reduced.
One of the more popular PLL designs used in the chips found in today's PLDs is the inclusion of a PLL to remove the insertion delay of their internal clock trees. Such designs allow better clock-to-out values on the outputs of the PCM, as well as improved setup and hold requirements on the inputs. However, this popular design is not well-suited for use in high frequency applications, such as those requiring clock speeds in excess of 125 MHZ. Specifically, in such designs, delays inside the chip containing the PCM that are not reduced or eliminated by the PLL circuit of the PCM still hamper high frequency uses since such delays are typically exacerbated when applied to high frequency applications. Another popular design includes the use of clock forwarding, which requires all the separate chips to source a clock along with the data. While beneficial in numerous applications, this design is not well-suited for use in SSRAM and SDRAM applications since those applications require the clock to be single-sourced externally.
Accordingly, what is needed in the art is a better way to compensate for timing variations encountered when a single-sourced board clock is used in high frequency applications.